The invention relates to a thin film transistor-liquid crystal display (TFT-LCD) device, and more particularly, to a testing wiring structure of a TFT array motherboard and a method for forming the same.
In recent years, TFT-LCD devices, which are of small volume, light weight, low power consumption and free of radiation, have gradually prevailed in the market of flat panel display devices. In general, a TFT-LCD device comprises a thin film transistor (TFT) array substrate and a color filter substrate that are maintained in parallel with a gap therebetween. Sandwiched between the TFT array substrate and the color filter substrate is a liquid crystal layer that varies its optical characteristics in response to the electrical field applied thereon. A TFT-LCD device can have an array including up to millions of pixels, and each pixel is controlled with a TFT as a switching device so as to display mages.
FIG. 1 is a schematic layout view of a conventional testing wiring structure of a TFT array motherboard. As shown in FIG. 1, a motherboard 100 comprises a plurality of panels 11, for example, four panels 11. After manufacturing and testing, the motherboard 100 is separated to be individual panels for assemble. On one side of a pixel region where the panels are formed, there are disposed testing wirings 2 for respective pixel regions. Each pixel region is provided with two testing wirings, which are connected to odd gate lines and even gate lines, respectively. During the testing of TFT pixel regions on the TFT array motherboard, a testing tool applies gate scan signals to respective panels through pin-contacting pads 10 and testing wirings 2, and similarly, the testing tool applies data scan signals to the panels of the motherboard 100 through another set of pin-contacting pads 10 and testing wirings 2. In order to reduce the testing time, pin-contacting pads 10 for two or more panels are located in a same region, and thus the testing tool can test two or more panels each time. The testing efficiency can be improved. Testing signals are transmitted to panels through testing wirings 2 in connection with the pin-contacting pads 10, realizing the testing on the panels in the TFT array motherboard. For the purpose of testing two or more panels with one set of pin-contacting pads 10 and maximizing the utilization efficiency of the motherboard, the space between panels is set to be very small, resulting in difficulties in routing the testing wirings. As shown with the dashed circular region in FIG. 1, the testing wirings generally give rise to an intersecting structure.
FIG. 2 is a schematic enlarged view of the dashed circular region in FIG. 1, showing the intersecting structure of the testing wirings. With reference to FIG. 2, a gate layer metallic testing wiring 3 intersects a drain layer metallic testing wiring 4, with the testing wiring 4 being formed above the testing wiring 3. The gate layer metallic testing wiring 3 is on the same layer as the gate electrodes of the TFTs, and the drain layer metallic testing wiring 4 is on the same layer as the drain and source electrodes of the TFTs. Both the testing wiring 3 and 4 are formed through a patterning process. Due to problems originating from the process, the intersecting region as shown in FIG. 2 may be broken down by electrostatic discharge (ESD), thus adversely affecting the testing on the panels. FIG. 3 is a schematic enlarged view of the dashed circular region in FIG. 1, showing another intersecting structure of the testing wirings. Also, a gate layer metallic testing wiring 3 intersects a pixel electrode layer testing wiring 5 with the latter being formed above the former. The gate layer metallic testing wiring 3 is on the same layer as the gate electrodes of the TFTs, and the pixel electrode layer testing wiring 5 is on the same layer as the pixel electrodes of the pixels. Compared with the drain layer metallic testing wiring 4, the pixel electrode layer testing wiring 5 is positioned above a passivation layer that is formed on the source and drain electrodes, and thus it is less likely to incur an electrostatic breakdown. Via holes 6 are formed in both ends of the pixel electrode layer testing wiring 5 such that the pixel electrode layer testing wiring 5 can be connected through the via holes 6 to the drain layer metallic testing wiring 4 in a non-intersecting region. Since the pixel electrode layer testing wiring 5 is far away from the gate layer metallic testing wiring 3, a resistance to the electrostatic breakdown is enhanced. However, even when the wiring structure shown in FIG. 3 is employed, there is a possibility of occurrence of electrostatic breakdown, and thus the electrical testing of the panels can not be performed successfully, undesirably affecting the manufacture of the TFT-LCD device.